1. Field of the Invention
The present invention relates to a charge eliminating mechanism for a stage, and a testing apparatus. More specifically, the present invention relates to a charge eliminating mechanism for a stage, which prevents any damage to a work-to-be-processed when testing the electrical characteristics of the work-to-be-processed, and a testing apparatus.
2. Description of the Related Art
A process for processing a work-to-be-processed (e.g., a semiconductor manufacturing process) has a step of testing a plurality of semiconductor elements (to be referred to as “devices” hereinafter) formed on a wafer-like substrate. As shown in, e.g., FIGS. 3A and 3B, a testing apparatus which performs this step can have a loader chamber 1 to transport wafers W stored in a cassette C one by one, and a prober chamber 2 adjacent to the loader chamber 1 to test the electrical characteristics of the devices.
As shown in FIGS. 3A and 3B, the loader chamber 1 can have a wafer transporting mechanism 3 which transports the wafers W one by one, and a rough positioning mechanism (to be referred to as a “sub chuck” hereinafter) 4 which aligns the direction of the wafer W transported by the wafer transporting mechanism 3.
The prober chamber 2 can have a stage 5 which moves in three-axis directions (X, Y, and Z directions) with the wafer W placed thereon and rotates in the forward and reverse directions along a θ direction, a probe card 6 arranged above the stage 5, and a positioning mechanism (to be referred to as an “alignment mechanism” hereinafter) 7 which aligns probes 6A of the probe card 6 and the wafer W on the stage 5 with each other.
The probe card 6 is fixed to a head plate 8 of the prober chamber 2. A test head T is arranged on the head plate 8. The test head T electrically connects the probe card 6 to an external tester.
When testing the electrical characteristics of devices formed on the wafer W, the wafer transporting mechanism 3 picks up the wafer W from the cassette C and places it on the stage 5 in the prober chamber 2. While the wafer transporting mechanism 3 transports the wafer W, the wafer W is aligned in a given direction on the sub chuck 4. In the prober chamber 2, the stage 5 is moved in the X, Y, and θ directions, so that the wafer W and probes 6A are aligned through the alignment mechanism 7. The stage 5 moves in the X and Y directions to position the first device immediately under the probes 6A. After that, the stage 5 moves upward in the Z direction, so that the device and the probes 6A are brought into electrical contact with each other. After the stage further overdrives, the electrical characteristics of the device are tested. After the test, the stage 5 moves downward, and the stage 5 repeats index feeding of the wafer W, so that the electrical characteristics of the plurality of devices formed on the wafer W are tested. After these devices are tested, the wafer transporting mechanism 3 returns the wafer W to the original position in the cassette C. The above operation is repeated to test the electrical characteristics of the devices formed on the next wafer W.